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pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 remote 8-bit i 2 c and smbus low-power i/o expander with interrupt output and configuration registers check for samples: pca9534a 1 features ? low standby current consumption of ? polarity inversion register 1 m a max ? internal power-on reset ? i 2 c to parallel port expander ? power-up with all channels configured as ? open-drain active-low interrupt output inputs ? operating power-supply voltage range of ? no glitch on power-up 2.3 v to 5.5 v ? noise filter on scl/sda inputs ? 5-v tolerant i/o ports ? latched outputs with high-current drive ? 400-khz fast i 2 c bus maximum capability for directly driving leds ? three hardware address pins allow up to ? latch-up performance exceeds 100 ma per eight devices on the i 2 c/smbus jesd 78, class ii ? allows up to 16 devices on the i 2 c/smbus ? esd protection exceeds jesd 22 when used in conjunction with the pca9534 ? 2000-v human-body model (a114-a) see table 1 for i 2 c expander offerings ? 200-v machine model (a115-a) ? input/output configuration register ? 1000-v charged-device model (c101) description/ordering information this 8-bit i/o expander for the two-line bidirectional bus (i 2 c) is designed for 2.3-v to 5.5-v v cc operation. it provides general-purpose remote i/o expansion for most microcontroller families via the i 2 c interface [serial clock (scl), serial data (sda)]. the pca9534a consists of one 8-bit configuration (input or output selection), input port, output port, and polarity inversion (active high or active low) register. at power on, the i/os are configured as inputs. however, the system master can enable the i/os as either inputs or outputs by writing to the i/o configuration bits. the data for each input or output is kept in the corresponding input or output register. the polarity of the input port register can be inverted with the polarity inversion register. all registers can be read by the system master. the system master can reset the pca9534a in the event of a timeout or other improper operation by utilizing the power-on reset feature, which puts the registers in their default state and initializes the i 2 c/smbus state machine. the pca9534a open-drain interrupt ( int) output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2006 ? 2010, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. db, dbq, dgv, dw, or pw package (top view) 12 3 4 5 6 7 8 1615 14 13 12 11 10 9 a0a1 a2 p0 p1 p2 p3 gnd v cc sdascl int p7p6 p5 p4 rgv package (top view) 16 6 8 2 10 p7 p5 4 3 1 7 5 12 11 9 13 14 15 sda a0 a1 p6 int scl p3 gnd p4 a2 p0p1 p2 rgt package (top view) 16 6 8 2 10 p7 p 5 4 3 1 7 5 12 11 9 13 14 15 s d a a 0 a 1 p6 int scl p 3 g nd p 4 a2 p0 p1 p2 v cc v cc
pca9534a scps141f ? september 2006 ? revised june 2010 www.ti.com int can be connected to the interrupt input of a microcontroller. by sending an interrupt signal on this line, the remote i/o can inform the microcontroller if there is incoming data on its ports without having to communicate via the i 2 c bus. thus, the pca9534a can remain a simple slave device. the device ' s outputs (latched) have high-current drive capability for directly driving leds. it has low current consumption. three hardware pins (a0, a1, and a2) are used to program and vary the fixed i 2 c address and allow up to eight devices to share the same i 2 c bus or smbus. the pca9534a is pin-to-pin and i 2 c address compatible with the pcf8574a. however, software changes are required due to the enhancements in the pca9534a over the pcf8574a. the pca9534a is a low-power version of the pca9554a. the only difference between the pca9534a and pca9554a is that the pca9534a eliminates an internal i/o pullup resistor, which dramatically reduces power consumption in the standby mode when the i/os are held low. the pca9534a and pca9534 are identical, except for their fixed i 2 c address. this allows for up to 16 of these devices (8 of each) on the same i 2 c bus. ordering information t a package (1) (2) orderable part number top-side marking qfn ? rgt reel of 3000 pca9534argtr zvj qfn ? rgv reel of 2500 pca9534argvr pd534a qsop ? dbq reel of 2500 pca9534adbqr pda534a tube of 40 pca9534adw soic ? dw pca9534a reel of 2000 pca9534adwr ? 40 c to 85 c reel of 2000 pca9534adbr ssop ? db pda534a tube of 80 pca9534adb tube of 90 pca9534apw tssop ? pw pd534a reel of 2000 pca9534apwr tvsop ? dgv reel of 2000 pca9534adgvr pd534a (1) package drawings, thermal data, and symbolization are available at www.ti.com/packaging . (2) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com . 2 submit documentation feedback copyright ? 2006 ? 2010, texas instruments incorporated product folder link(s): pca9534a
pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 table 1. i 2 c expander offerings max v cc no. of interrupt reset configuration 5-v push-pull open-drain i 2 c device comment frequency range gpios output input registers tolerant i/o type i/o type address power on reset, t f (fall time) > 100 ms and t r (ramp time) < tca6408 400 0100 00x 1.65 to 5.5 8 yes yes yes yes yes no 10 ms unrestricted power on reset ramp/fall time. both t f (fall tca6408 400 0100 00x 1.65 to 5.5 8 yes yes yes yes yes no time) and trt (ramp time) can be between 0.1 ms and 2000 ms power on reset, t f (fall time) > 100 ms and trt (ramp tca6416 400 0100 00x 1.65 to 5.5 16 yes yes yes yes yes no time) < 10 ms unrestricted power on reset ramp/fall time. both t f (fall tca6416a 400 0100 00x 1.65 to 5.5 16 yes yes yes yes yes no time) and trt (ramp time) can be between 0.1 ms and 2000ms power on reset, t f (fall time) > 100 ms and trt (ramp tca6424 400 0100 00x 1.65 to 5.5 24 yes yes yes yes yes no time) < 10 ms tca9535 400 0100 xxx 1.65 to 5.5 16 yes no yes yes yes no tca9539 400 1110 1xx 1.65 to 5.5 16 yes yes yes yes yes no tca9555 400 0100 xxx 1.65 to 5.5 16 yes no yes yes yes no yes yes one open drain output; eight push pull outputs pca6107 400 0011 xxx 2.3 to 5.5 8 yes yes yes yes p1 D p7 bits p0 bit pca9534 has a different slave address as the pca9534a, allowing up to 16 devices ' 9534 type devices on the same pca9534 400 0100 xxx 2.3 to 5.5 8 yes no yes yes yes no i 2 c bus pca9534a has a different slave address as the pca9534, allowing up to 16 devices ' 9534 type devices on the same pca9534a 400 0111 xxx 2.3 to 5.5 8 yes no yes yes yes no i 2 c bus pca9535 400 0100 xxx 2.3 to 5.5 16 yes no yes yes yes no pca9536 400 1000 001 2.3 to 5.5 4 no no yes yes yes no pca9538 400 1110 0xx 2.3 to 5.5 8 yes yes yes yes yes no pca9539 400 1110 1xx 2.3 to 5.5 16 yes yes yes yes yes no pca9554 400 0100 xxx 2.3 to 5.5 8 yes no yes yes yes no pca9554a 400 0111 xxx 2.3 to 5.5 8 yes no yes yes yes no pca9555 400 0100 xxx 2.3 to 5.5 16 yes no yes yes yes no pca9557 400 0011 xxx 2.3 to 5.5 8 no yes yes yes yes yes pca8574 has a different slave address as the pca8574a, allowing up to 16 devices ' 9534 type devices on the same pcf8574 400 0100 xxx 2.5 to 6.0 8 yes no no yes yes no i 2 c bus pca8574a has a different slave address as the pca8574, allowing up to 16 devices ' 9534 type devices on the same pcf8574a 400 0111 xxx 2.5 to 6.0 8 yes no no yes yes no i 2 c bus pcf8575 400 0100 xxx 2.5 to 5.5 16 yes no no yes yes no pcf8575c 400 0100 xxx 4.5 to 5.5 16 yes no no yes no yes copyright ? 2006 ? 2010, texas instruments incorporated submit documentation feedback 3 product folder link(s): pca9534a
pca9534a scps141f ? september 2006 ? revised june 2010 www.ti.com table 2. terminal functions no. qsop (dbq), soic (dw), qfn (rgt) name description ssop (db), and tssop (pw), and qfn (rgv) tvsop (dgv) 1 15 a0 address input. connect directly to v cc or ground. 2 16 a1 address input. connect directly to v cc or ground. 3 1 a2 address input. connect directly to v cc or ground. 4 2 p0 p-port input/output. push-pull design structure. 5 3 p1 p-port input/output. push-pull design structure. 6 4 p2 p-port input/output. push-pull design structure. 7 5 p3 p-port input/output. push-pull design structure. 8 6 gnd ground 9 7 p4 p-port input/output. push-pull design structure. 10 8 p5 p-port input/output. push-pull design structure. 11 9 p6 p-port input/output. push-pull design structure. 12 10 p7 p-port input/output. push-pull design structure. 13 11 int interrupt output. connect to v cc through a pullup resistor. 14 12 scl serial clock bus. connect to v cc through a pullup resistor. 15 13 sda serial data bus. connect to v cc through a pullup resistor. 16 14 v cc supply voltage logic diagram (positive logic) a. pin numbers shown are for db, dbq, dgv, dw, or pw package. b. all i/os are set to inputs at reset. 4 submit documentation feedback copyright ? 2006 ? 2010, texas instruments incorporated product folder link(s): pca9534a 14 i/o port shift register 8 bits lp filter interrupt logic inputfilter 15 power-on reset read pulse w rite pulse 2 1 1316 8 gnd v cc sda scl a1 a0 int i 2 c bus control p7?p0 3 a2
pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 simplified schematic of p0 to p7 a. at power-on reset, all registers return to default values. i/o port when an i/o is configured as an input, fets q1 and q2 are off, creating a high-impedance input. the input voltage may be raised above v cc to a maximum of 5.5 v. if the i/o is configured as an output, q1 or q2 is enabled, depending on the state of the output port register. in this case, there are low-impedance paths between the i/o pin and either v cc or gnd. the external voltage applied to this i/o pin should not exceed the recommended levels for proper operation. i 2 c interface the bidirectional i 2 c bus consists of the serial clock (scl) and serial data (sda) lines. both lines must be connected to a positive supply through a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. i 2 c communication with this device is initiated by a master sending a start condition, a high-to-low transition on the sda input/output while the scl input is high (see figure 1 ). after the start condition, the device address byte is sent, msb first, including the data direction bit (r/w). after receiving the valid address byte, this device responds with an acknowledge (ack), a low on the sda input/output during the high of the ack-related clock pulse. the address inputs (a0 ? a2) of the slave device must not be changed between the start and the stop conditions. on the i 2 c bus, only one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (start or stop) (see figure 2 ). copyright ? 2006 ? 2010, texas instruments incorporated submit documentation feedback 5 product folder link(s): pca9534a data from shift register data from shift register w rite configuration pulse w rite pulse read pulse w rite polarity pulse data from shift register output port register configuration register input port register polarity inversion register polarityregister data input portregister data gnd esd protectiondiode p0 to p7 v cc output portregister data q1 q2 dc k ff qq dc k ff qq dc k ff qq dc k ff qq t o int
pca9534a scps141f ? september 2006 ? revised june 2010 www.ti.com a stop condition, a low-to-high transition on the sda input/output while the scl input is high, is sent by the master (see figure 1 ). any number of data bytes can be transferred from the transmitter to receiver between the start and the stop conditions. each byte of eight bits is followed by one ack bit. the transmitter must release the sda line before the receiver can send an ack bit. the device that acknowledges must pull down the sda line during the ack clock pulse so that the sda line is stable low during the high pulse of the ack-related clock period (see figure 3 ). when a slave receiver is addressed, it must generate an ack after each byte is received. similarly, the master must generate an ack after each byte that it receives from the slave transmitter. setup and hold times must be met to ensure proper operation. a master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (nack) after the last byte has been clocked out of the slave. this is done by the master receiver by holding the sda line high. in this event, the transmitter must release the data line to enable the master to generate a stop condition. figure 1. definition of start and stop conditions figure 2. bit transfer figure 3. acknowledgment on i 2 c bus 6 submit documentation feedback copyright ? 2006 ? 2010, texas instruments incorporated product folder link(s): pca9534a sda scl start condition s stop condition p sda scl data line stable; data v alid change of data allowed data output by t ransmitter scl from master start condition s 1 2 8 9 data output by receiver clock pulse for acknowledgment nack ack
pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 table 3. interface definition bit byte 7 (msb) 6 5 4 3 2 1 0 (lsb) i 2 c slave address l h h h a2 a1 a0 r/ w px i/o data bus p7 p6 p5 p4 p3 p2 p1 p0 device address figure 4 shows the address byte of the pca9534a. figure 4. pca9534a address table 4. address reference inputs i 2 c bus slave address a2 a1 a0 l l l 56 (decimal), 38 (hexadecimal) l l h 57 (decimal), 39 (hexadecimal) l h l 58 (decimal), 3a (hexadecimal) l h h 59 (decimal), 3b (hexadecimal) h l l 60 (decimal), 3c (hexadecimal) h l h 61 (decimal), 3d (hexadecimal) h h l 62 (decimal), 3e (hexadecimal) h h h 63 (decimal), 3f (hexadecimal) the last bit of the slave address defines the operation (read or write) to be performed. when it is high (1), a read is selected, while a low (0) selects a write operation. control register and command byte following the successful acknowledgment of the address byte, the bus master sends a command byte which is stored in the control register in the pca9534a. two bits of this command byte state the operation (read or write) and the internal register (input, output, polarity inversion or configuration) that will be affected. this register can be written or read through the i 2 c bus. the command byte is sent only during a write transmission. once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. figure 5. control register bits copyright ? 2006 ? 2010, texas instruments incorporated submit documentation feedback 7 product folder link(s): pca9534a 0 1 1 1 a1 a2 a0 slave address r/w fixed hardware selectable 0 0 0 0 b1 b0 0 0
pca9534a scps141f ? september 2006 ? revised june 2010 www.ti.com table 5. command byte control command power-up register bits register protocol byte (hex) default b1 b0 0 0 0x00 input port read byte xxxx xxxx 0 1 0x01 output port read/write byte 1111 1111 1 0 0x02 polarity inversion read/write byte 0000 0000 1 1 0x03 configuration read/write byte 1111 1111 register descriptions the input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the configuration register. it only acts on read operation. writes to these registers have no effect. the default value, x, is determined by the externally applied logic level. before a read operation, a write transmission is sent with the command byte to let the i 2 c device know that the input port register will be accessed next. table 6. register 0 (input port register) bit i7 i6 i5 i4 i3 i2 i1 i0 default x x x x x x x x the output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the configuration register. bit values in this register have no effect on pins defined as inputs. in turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. table 7. register 1 (output port register) bit o7 o6 o5 o4 o3 o2 o1 o0 default 1 1 1 1 1 1 1 1 the polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the configuration register. if a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. if a bit in this register is cleared (written with a 0), the corresponding port pin original polarity is retained. table 8. register 2 (polarity inversion register) bit n7 n6 n5 n4 n3 n2 n1 n0 default 0 0 0 0 0 0 0 0 the configuration register (register 3) configures the directions of the i/o pins. if a bit in this register is set to 1, the corresponding port pin is enabled as an input with high-impedance output driver. if a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. table 9. register 3 (configuration register) bit c7 c6 c5 c4 c3 c2 c1 c0 default 1 1 1 1 1 1 1 1 power-on reset when power (from 0 v) is applied to v cc , an internal power-on reset holds the pca9534a in a reset condition until v cc has reached v por . at that point, the reset condition is released and the pca9534a registers and i 2 c/smbus state machine initialize to their default states. after that, v cc must be lowered to below 0.2 v and then back up to the operating voltage for a power-reset cycle. 8 submit documentation feedback copyright ? 2006 ? 2010, texas instruments incorporated product folder link(s): pca9534a
pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 interrupt output ( int) an interrupt is generated by any rising or falling edge of the port inputs in the input mode. after time, t iv , the signal int is valid. resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt. resetting occurs in the read mode at the acknowledge (ack) or not acknowledge (nack) bit after the rising edge of the scl signal. interrupts that occur during the ack or nack clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. each change of the i/os after resetting is detected and is transmitted as int. writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. changing an i/o from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the input port register. because each 8-pin port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1 or vice versa. the int output has an open-drain structure and requires pullup resistor to v cc . bus transactions data is exchanged between the master and pca9534a through write and read commands. writes data is transmitted to the pca9534a by sending the device address and setting the least-significant bit to a logic 0 (see figure 4 for device address). the command byte is sent after the address and determines which register receives the data that follows the command byte (see figure 6 and figure 7 ). there is no limitation on the number of data bytes sent in one write transmission. figure 6. write to output port register < br/ > figure 7. write to configuration or polarity inversion registers copyright ? 2006 ? 2010, texas instruments incorporated submit documentation feedback 9 product folder link(s): pca9534a scl start condition data 1 v alid sda w rite to port data out from port r/w ack from slave ack from slave ack from slave 1 9 8 7 6 5 4 3 2 data 1 1 a2 0 1 s 1 1 a1 a0 0 a 0 0 0 0 0 0 0 a a p t pv data to port command byte slave address data 1/0 a2 0 1 s 1 1 a1 a0 0 a 1 0 0 0 0 0 0 a a p scl sda data to register start condition r/w ack from slave ack from slave ack from slave 1 9 8 7 6 5 4 3 2 data to register command byte slave address
pca9534a scps141f ? september 2006 ? revised june 2010 www.ti.com reads the bus master first must send the pca9534a address with the least-significant bit set to a logic 0 (see figure 4 for device address). the command byte is sent after the address and determines which register is accessed. after a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. data from the register defined by the command byte then is sent by the pca9534a (see figure 8 and figure 9 ). after a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. data is clocked into the register on the rising edge of the ack clock pulse. there is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. figure 8. read from register < br/ > a. this figure assumes that the command byte has previously been programmed with 00h. b. transfer of data can be stopped at any moment by a stop condition. c. this figure eliminates the command byte transfer, a restart and slave address call between the initial slave address call and the actual data transfer from the p port. see figure 8 for these details. figure 9. read input port register 10 submit documentation feedback copyright ? 2006 ? 2010, texas instruments incorporated product folder link(s): pca9534a a2 0 1 s 1 1 a1 a0 0 a a data from register slave address slave address r/w ack from slave command byte ack from slave s a2 0 1 1 1 a1 a0 r/w 1 a data a ack from master data data from register nack from master na p last byte ack from slave scl sda int start condition r/w read from port data into port stopcondition ack from master nack from master ack from slave data from port slave address data from port 1 9 8 7 6 5 4 3 2 a2 0 1 s 1 1 a1 a0 1 a data 1 data 4 a na p data 2 data 3 data 4 t iv t ph t ps t ir data 5
pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage range ? 0.5 6 v v i input voltage range (2) ? 0.5 6 v v o output voltage range (2) ? 0.5 6 v i ik input clamp current v i < 0 ? 20 ma i ok output clamp current v o < 0 ? 20 ma i iok input/output clamp current v o < 0 or v o > v cc 20 ma i ol continuous output low current v o = 0 to v cc 50 ma i oh continuous output high current v o = 0 to v cc ? 50 ma continuous current through gnd ? 250 i cc ma continuous current through v cc 160 db package 82 dbq package 90 dgv package 86 dw package 46 q ja package thermal impedance (3) c/w n package 67 pw package 88 rgt package tbd rgv package 51 t stg storage temperature range ? 65 150 c (1) stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operating conditions " is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) the package thermal impedance is calculated in accordance with jesd 51-7. recommended operating conditions min max unit v cc supply voltage 2.3 5.5 v scl, sda 0.7 v cc 5.5 v ih high-level input voltage v a2 ? a0, p7 ? p0 2 5.5 scl, sda ? 0.5 0.3 v cc v il low-level input voltage v a2 ? a0, p7 ? p0 ? 0.5 0.8 i oh high-level output current p7 ? p0 ? 10 ma i ol low-level output current p7 ? p0 25 ma t a operating free-air temperature ? 40 85 c copyright ? 2006 ? 2010, texas instruments incorporated submit documentation feedback 11 product folder link(s): pca9534a
pca9534a scps141f ? september 2006 ? revised june 2010 www.ti.com electrical characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ (1) max unit v ik input diode clamp voltage i i = ? 18 ma 2.3 v to 5.5 v ? 1.2 v v por power-on reset voltage v i = v cc or gnd, i o = 0 v por 1.5 1.65 v 2.3 v 1.8 3 v 2.6 i oh = ? 8 ma 4.5 v 4.1 4.75 v 4.1 v oh p-port high-level output voltage (2) v 2.3 v 1.7 3 v 2.5 i oh = ? 10 ma 4.5 v 4 4.75 v 4 sda v ol = 0.4 v 2.3 v to 5.5 v 3 8 2.3 v 8 10 3 v 8 14 v ol = 0.5 v 4.5 v 8 17 4.75 v 8 35 i ol p port (3) ma 2.3 v 10 13 3 v 10 19 v ol = 0.7 v 4.5 v 10 24 4.75 v 10 45 int v ol = 0.4 v 2.3 v to 5.5 v 3 10 scl, sda 1 i i v i = v cc or gnd 2.3 v to 5.5 v m a a2 ? a0 1 i ih p port v i = v cc 2.3 v to 5.5 v 1 m a i il p port v i = gnd 2.3 v to 5.5 v ? 1 m a 5.5 v 104 175 v i = v cc or gnd, i o = 0, 3.6 v 50 90 i/o = inputs, f scl = 400 khz 2.7 v 20 65 operating mode 5.5 v 60 150 v i = v cc or gnd, i o = 0, i cc 3.6 v 15 40 m a i/o = inputs, f scl = 100 khz 2.7 v 8 20 5.5 v 0.25 1 v i = gnd, i o = 0, standby mode 3.6 v 0.2 0.9 i/o = inputs, f scl = 0 khz 2.7 v 0.1 0.8 one input at v cc ? 0.6 v, 2.3 v to 5.5 v 1.5 other inputs at v cc or gnd additional current in standby i cc ma mode all led i/os at v i = 4.3 v, 5.5 v 1 f scl = 0 khz c i scl v i = v cc or gnd 2.3 v to 5.5 v 4 5 pf sda 5.5 6.5 c io v io = v cc or gnd 2.3 v to 5.5 v pf p port 8 9.5 (1) all typical values are at nominal supply voltage (2.5-v, 3.3-v, or 5-v v cc ) and t a = 25 c. (2) the total current sourced by all i/os must be limited to 85 ma. (3) each i/o must be externally limited to a maximum of 25 ma, and the p port (p7 ? p0) must be limited to a maximum current of 200 ma. 12 submit documentation feedback copyright ? 2006 ? 2010, texas instruments incorporated product folder link(s): pca9534a
pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 i 2 c interface timing requirements over operating free-air temperature range (unless otherwise noted) (see figure 10 ) standard mode fast mode i 2 c bus i 2 c bus unit min max min max f scl i 2 c clock frequency 0 100 0 400 khz t sch i 2 c clock high time 4 0.6 m s t scl i 2 c clock low time 4.7 1.3 m s t sp i 2 c spike time 50 50 ns t sds i 2 c serial-data setup time 250 100 ns t sdh i 2 c serial-data hold time 0 0 ns t icr i 2 c input rise time 1000 20 + 0.1c b (1) 300 ns t icf i 2 c input fall time 300 20 + 0.1c b (1) 300 ns t ocf i 2 c output fall time 10-pf to 400-pf bus 300 20 + 0.1c b (1) 300 ns t buf i 2 c bus free time between stop and start 4.7 1.3 m s t sts i 2 c start or repeated start condition setup 4.7 0.6 m s t sth i 2 c start or repeated start condition hold 4 0.6 m s t sps i 2 c stop condition setup 4 0.6 m s t vd(data) valid data time scl low to sda output valid 300 50 ns ack signal from scl low to t vd(ack) valid data time of ack condition 0.3 3.45 0.1 0.9 m s sda (out) low c b i 2 c bus capacitive load 400 400 ns (1) c b = total capacitive of one bus in pf switching characteristics over operating free-air temperature range (unless otherwise noted) (see figure 11 and figure 12 ) standard mode fast mode from to i 2 c bus i 2 c bus parameter unit (input) (output) min max min max t iv interrupt valid time p port int 4 4 m s t ir interrupt reset delay time scl int 4 4 m s t pv output data valid scl p7 ? p0 200 200 ns t ps input data setup time p port scl 100 100 ns t ph input data hold time p port scl 1 1 m s copyright ? 2006 ? 2010, texas instruments incorporated submit documentation feedback 13 product folder link(s): pca9534a
pca9534a scps141f ? september 2006 ? revised june 2010 www.ti.com typical characteristics supply current quiescent supply current vs vs temperature temperature supply current supply current vs vs supply voltage number of i/os held low 14 submit documentation feedback copyright ? 2006 ? 2010, texas instruments incorporated product folder link(s): pca9534a 0 5 10 15 20 25 30 35 -40 -15 10 35 60 85 t a C free-air temperature C c i cc C supply current C na v cc = 2.5 v v cc = 3.3 v v cc = 5 v scl = v cc 0 5 10 15 20 25 30 35 40 45 50 55 -40 -15 10 35 60 85 t a C free-air temperature C c i cc C supply current C a v cc = 2.5 v v cc = 3.3 v v cc = 5 v f scl = 400 khz i/os unloaded 0 10 20 30 40 50 60 70 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v cc C supply voltage C v i cc C supply current C a f scl = 400 khz i/os unloaded 0 50 100 150 200 250 300 350 400 450 500 550 600 0 1 2 3 4 5 6 7 8 number of i/os held low i cc C supply current C a t a = C40c v cc = 5 v t a = 25c t a = 85c
pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 typical characteristics (continued) i/o output low voltage i/o sink current vs vs temperature output low voltage i/o sink current i/o sink current vs vs output low voltage output low voltage copyright ? 2006 ? 2010, texas instruments incorporated submit documentation feedback 15 product folder link(s): pca9534a 0 25 50 75 100 125 150 175 200 225 250 275 300 -40 -15 10 35 60 85 t a C free-air temperature C c v ol C output low voltage C mv v cc = 5 v, i sink = 10 ma v cc = 2.5 v, i sink = 10 ma v cc = 2.5 v, i sink = 1 ma v cc = 5 v, i sink = 1 ma 0 5 10 15 20 25 30 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 v ol C output low voltage C v i sink C i/o sink current C ma t a = C40c v cc = 2.5 v t a = 25c t a = 85c 0 5 10 15 20 25 30 35 40 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 v ol C output low voltage C v i sink C i/o sink current C ma t a = C40c v cc = 3.3 v t a = 25c t a = 85c 0 5 10 15 20 25 30 35 40 45 50 55 60 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 v ol C output low voltage C v i sink C i/o sink current C ma t a = C40c v cc = 5 v t a = 25c t a = 85c
pca9534a scps141f ? september 2006 ? revised june 2010 www.ti.com typical characteristics (continued) i/o output high voltage i/o source current vs vs temperature output high voltage i/o source current i/o source current vs vs output high voltage output high voltage 16 submit documentation feedback copyright ? 2006 ? 2010, texas instruments incorporated product folder link(s): pca9534a 0 25 50 75 100 125 150 175 200 225 250 275 -40 -15 10 35 60 85 t a C free-air temperature C c (v cc C v oh ) C output high voltage C mv v cc = 5 v, i ol = 10 ma v cc = 2.5 v, i ol = 10 ma v cc = 5 v, i ol = 1 ma v cc = 2.5 v, i ol = 1 ma 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (v cc C v oh ) C output high voltage C v i source C i/o source current C ma t a = C40c v cc = 5 v t a = 25c t a = 85c 0 5 10 15 20 25 30 35 40 45 50 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (v cc C v oh ) C output high voltage C v i source C i/o source current C ma t a = C40c v cc = 3.3 v t a = 25c t a = 85c 0 5 10 15 20 25 30 35 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 (v cc C v oh ) C output high voltage C v i source C i/o source current C ma t a = C40c v cc = 2.5 v t a = 25c t a = 85c
pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 typical characteristics (continued) output high voltage vs supply voltage copyright ? 2006 ? 2010, texas instruments incorporated submit documentation feedback 17 product folder link(s): pca9534a 0 1 2 3 4 5 6 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v cc C supply voltage C v v oh C output high voltage C v i oh = C10 ma i oh = C8 ma t a = 25c
pca9534a scps141f ? september 2006 ? revised june 2010 www.ti.com parameter measurement information a. c l includes probe and jig capacitance. b. all inputs are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , t r /t f 30 ns. c. all parameters and waveforms are not applicable to all devices. figure 10. i 2 c interface load circuit and voltage waveforms 18 submit documentation feedback copyright ? 2006 ? 2010, texas instruments incorporated product folder link(s): pca9534a r l = 1 k w v cc c l = 50 pf (see note a) t buf t icr t sth t sds t sdh t icf t icr t scl t sch t sts t phl t plh 0.3 v cc stop condition t sps repeat start condition start orrepeat start condition scl sda start condition (s) address bit 7 (msb) data bit 10 (lsb) stop condition (p) three bytes for complete device programming sda load configura tion volt age w aveforms t icf stop condition (p) t sp dut sda 0.7 v cc 0.3 v cc 0.7 v cc r/w bit 0 (lsb) ack (a) data bit 07 (msb) address bit 1 address bit 6 byte description 1 i 2 c address 2, 3 p-port data
pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 parameter measurement information (continued) a. c l includes probe and jig capacitance. b. all inputs are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , t r /t f 30 ns. c. all parameters and waveforms are not applicable to all devices. figure 11. interrupt load circuit and voltage waveforms copyright ? 2006 ? 2010, texas instruments incorporated submit documentation feedback 19 product folder link(s): pca9534a a a a a s 0 1 1 1 a1 a2 a0 1 data 1 1 p data 2 start condition 8 bits (one data byte) from port data from port slave address r/w 8 7 6 5 4 3 2 1 t ir t ir t sps t iv address data 1 data 2 int data into port b b a a p n int r/w a t ir 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc int scl v iew b?b v iew a?a t iv r l = 4.7 k v cc c l = 100 pf (see note a) interrupt load configura tion dut int ack from slave ack from slave
pca9534a scps141f ? september 2006 ? revised june 2010 www.ti.com parameter measurement information (continued) a. c l includes probe and jig capacitance. b. t pv is measured from 0.7 v cc on scl to 50% i/o (pn) output. c. all inputs are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , t r /t f 30 ns. d. the outputs are measured one at a time, with one transition per measurement. e. all parameters and waveforms are not applicable to all devices. figure 12. p-port load circuit and voltage waveforms 20 submit documentation feedback copyright ? 2006 ? 2010, texas instruments incorporated product folder link(s): pca9534a p0 a 0.7 v cc 0.3 v cc scl p3 ??? ??? ??? ??? ??? t pv (see note b) slave ack unstable data last stable bit sda p n p n write mode (r/w = 0) p0 a 0.7 v cc 0.3 v cc scl p3 0.7 v cc 0.3 v cc t ps t ph read mode (r/w = 1) dut c l = 50 pf (see note a) p-port load configura tion pn 2 v cc 500 500
pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 parameter measurement information (continued) a. c l includes probe and jig capacitance. b. all inputs are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , t r /t f 30 ns. c. i/os are configured as inputs. d. all parameters and waveforms are not applicable to all devices. figure 13. reset load circuits and voltage waveforms copyright ? 2006 ? 2010, texas instruments incorporated submit documentation feedback 21 product folder link(s): pca9534a sda scl start ack or read cycle t w t rec reset 0.3 v cc v cc /2 t reset pn r l = 1 k v cc c l = 50 pf (see note a) sda load configura tion dut sda p-port load configura tion v cc /2 t reset dut c l = 50 pf (see note a) pn 2 v cc 500 500
pca9534a scps141f ? september 2006 ? revised june 2010 www.ti.com application information figure 14 shows an application in which the pca9534a can be used. a. device address is configured as 0111100 for this example. b. p0, p2, and p3 are configured as outputs. c. p1, p4, and p5 are configured as inputs. d. p6 and p7 are not used and must be configured as outputs. figure 14. typical application 22 submit documentation feedback copyright ? 2006 ? 2010, texas instruments incorporated product folder link(s): pca9534a a2a1 a0 sda scl int gnd gnd p6 p0p1 p2 p3 p4 p5 p7 int gnd v cc v cc (5 v) v cc 10 k 10 k 10 k 10 k 2 k 100 k ( 3) x 100 k 4.7 k master controller pca9534a int reset subsystem 2 (e.g., counter) subsystem 3 (e.g., alarm system) alarm controlled device (e.g., cbt device) enable a b subsystem 1 (e.g., temperature sensor) scl sda
pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 minimizing i cc when the i/o controls leds when the i/os are used to control leds, they normally are connected to v cc through a resistor as shown in figure 14 . because the led acts as a diode, when the led is off, the i/o v in is about 1.2 v less than v cc . the supply current, i cc , increases as v in becomes lower than v cc and is specified as i cc in electrical characteristics . for battery-powered applications, it is essential that the voltage of the i/o pins is greater than or equal to v cc when the led is off to minimize current consumption. figure 15 shows a high-value resistor in parallel with the led. figure 16 shows v cc less than the led supply voltage by at least 1.2 v. both of these methods maintain the i/o v in at or above v cc and prevents additional supply-current consumption when the led is off. figure 15. high-value resistor in parallel with the led figure 16. device supplied by a lower voltage power-on reset requirements in the event of a glitch or data corruption, pca9534a can be reset to its default conditions by using the power-on reset feature. power-on reset requires that the device go through a power cycle to be completely reset. this reset also happens when the device is powered on for the first time in an application. the two types of power-on reset are shown in figure 17 and figure 18 . figure 17. v cc is lowered below 0.2 v or 0 v and then ramped up to v cc copyright ? 2006 ? 2010, texas instruments incorporated submit documentation feedback 23 product folder link(s): pca9534a led 3.3 v 5 v ledx v cc v cc ramp-up re-ramp-up time to re-ramp time ramp-down v cc_rt v cc_rt v cc_ft v cc_trr_gnd led ledx v cc 100 k v cc
pca9534a scps141f ? september 2006 ? revised june 2010 www.ti.com figure 18. v cc is lowered below the por threshold, then ramped back up to v cc table 10 specifies the performance of the power-on reset feature for pca9534a for both types of power-on reset. table 10. recommended supply sequencing and ramp rates (1) parameter min typ max unit v cc_ft fall rate see figure 17 1 100 ms v cc_rt rise rate see figure 17 0.01 100 ms v cc_trr_gnd time to re-ramp (when v cc drops to gnd) see figure 17 0.001 ms v cc_trr_por50 time to re-ramp (when v cc drops to v por_min ? 50 mv) see figure 18 0.001 ms level that v ccp can glitch down to, but not cause a functional v cc_gh see figure 19 1.2 v disruption when v ccx_gw = 1 m s glitch width that will not cause a functional disruption when v cc_gw see figure 19 m s v ccx_gh = 0.5 v ccx v porf voltage trip point of por on falling v cc 0.767 1.144 v v porr voltage trip point of por on fising v cc 1.033 1.428 v (1) t a = ? 40 c to 85 c (unless otherwise noted) glitches in the power supply can also affect the power-on reset performance of this device. the glitch width (v cc_gw ) and height (v cc_gh ) are dependent on each other. the bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. figure 19 and table 10 provide more information on how to measure these specifications. figure 19. glitch width and glitch height v por is critical to the power-on reset. v por is the voltage level at which the reset condition is released and all the registers and the i 2 c/smbus state machine are initialized to their default states. the value of v por differs based on the v cc being lowered to or from 0. figure 20 and table 10 provide more details on this specification. 24 submit documentation feedback copyright ? 2006 ? 2010, texas instruments incorporated product folder link(s): pca9534a v cc time v cc_gh v cc_gw v cc ramp-up time to re-ramp time ramp-down v in drops below por levels v cc_rt v cc_ft v cc_trr_vpor50
pca9534a www.ti.com scps141f ? september 2006 ? revised june 2010 figure 20. v por interrupt requirements the expected performance of the interrupt feature is that int is to be cleared (de-asserted) when the input register is read or all inputs return to the last read values. int is also de-asserted when both of the following occur: ? the last i 2 c command byte (register pointer) written was 00h. this generally means the last operation with the device was a read of the input register, but the command byte may have been written with 00h without ever going on to read the input register. ? any other slave device on the i 2 c bus acknowledges an address byte with the r/ w bit set high. this occurs when reading any other valid device on the bus. in order to prevent int from de-asserting when another device is read on the i 2 c bus, the user needs to change the command byte to something other than 00 (hex) after a read operation to the device. copyright ? 2006 ? 2010, texas instruments incorporated submit documentation feedback 25 product folder link(s): pca9534a v cc v por v porf time por time
package option addendum www.ti.com 24-jun-2010 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) pca9534adb active ssop db 16 80 green (rohs & no sb/br) cu nipdau level-1-260c-unlim purchase samples pca9534adbg4 active ssop db 16 80 green (rohs & no sb/br) cu nipdau level-1-260c-unlim purchase samples pca9534adbr active ssop db 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim request free samples pca9534adbrg4 active ssop db 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim request free samples pca9534adgvr active tvsop dgv 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim request free samples pca9534adgvrg4 active tvsop dgv 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim request free samples pca9534adw active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim purchase samples pca9534adwg4 active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim purchase samples pca9534adwr active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim request free samples pca9534adwrg4 active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim request free samples pca9534apw active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim purchase samples pca9534apwg4 active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim purchase samples pca9534apwr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim request free samples pca9534apwrg4 active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim request free samples pca9534argtr active qfn rgt 16 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year request free samples pca9534argtrg4 active qfn rgt 16 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year request free samples pca9534argvr active vqfn rgv 16 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year request free samples
package option addendum www.ti.com 24-jun-2010 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) PCA9534ARGVRG4 active vqfn rgv 16 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year request free samples (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant pca9534adbr ssop db 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 q1 pca9534adgvr tvsop dgv 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 q1 pca9534adwr soic dw 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 q1 pca9534apwr tssop pw 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 pca9534argtr qfn rgt 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 pca9534argvr vqfn rgv 16 2500 330.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 package materials information www.ti.com 30-jul-2010 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) pca9534adbr ssop db 16 2000 346.0 346.0 33.0 pca9534adgvr tvsop dgv 16 2000 346.0 346.0 29.0 pca9534adwr soic dw 16 2000 346.0 346.0 33.0 pca9534apwr tssop pw 16 2000 346.0 346.0 29.0 pca9534argtr qfn rgt 16 3000 346.0 346.0 29.0 pca9534argvr vqfn rgv 16 2500 346.0 346.0 29.0 package materials information www.ti.com 30-jul-2010 pack materials-page 2

mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
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products www.dlp.com communications and www.ti.com/communications telecom dsp dsp.ti.com computers and www.ti.com/computers peripherals clocks and timers www.ti.com/clocks consumer electronics www.ti.com/consumer-apps interface interface.ti.com energy www.ti.com/energy logic logic.ti.com industrial www.ti.com/industrial power mgmt power.ti.com medical www.ti.com/medical microcontrollers microcontroller.ti.com security www.ti.com/security rfid www.ti-rfid.com space, avionics & www.ti.com/space-avionics-defense defense rf/if and zigbee? solutions www.ti.com/lprf video and imaging www.ti.com/video wireless www.ti.com/wireless-apps mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2010, texas instruments incorporated

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